GCVE-110-CERTCC-2018-631579

Advisory PublishedCVSS 6.8/10

Vulnetix · Advisory published May 8, 2018

In some circumstances, some operating systems or hypervisors may not expect or properly handle an Intel architecture hardware debug exception. The error appears to be due to developer interpretation of existing documentation for certain Intel architecture interrupt/exception instructions, namely MOV SS and POP SS.

Download JSON Open in Console

Risk Scores

CVSS 2.0

6.8/10

Medium · AV:N/AC:M/Au:N/C:P/I:P/A:P

certcc-cam

impact0population0exploitation0widely_known0score_current0ease_of_exploitation0

certcc-vrda

d1_direct_report1

certcc-cvss-temporal-env

temporal_score5.3remediation_levelOFreport_confidenceCenvironmental_score5.34188900402325target_distributionNDenvironmental_vectorCDP:ND/TD:ND/CR:ND/IR:ND/AR:ND

References

Hardware debug exception documentation may result in unexpected behavior

url

Hardware debug exception documentation may result in unexpected behavior

url

Hardware debug exception documentation may result in unexpected behavior

advisory

Browse GCVE Records

73,734 records in the GCVE database · Updated July 18, 2026

No matching records found.

Explore Further

Investigate this vulnerability in the interactive console or download the raw GCVE record.

Open in Console Download JSON