ALPINE-CVE-2023-46842
Record from OSV · Published May 16, 2024
Unlike 32-bit PV guests, HVM guests may switch freely between 64-bit and other modes. This in particular means that they may set registers used to pass 32-bit-mode hypercall arguments to values outside of the range 32-bit code would be able to set them to. When processing of hypercalls takes a considerable amount of time, the hypervisor may choose to invoke a hypercall continuation. Doing so involves putting (perhaps updated) hypercall arguments in respective registers. For guests not running in 64-bit mode this further involves a certain amount of translation of the values. Unfortunately internal sanity checking of these translated values assumes high halves of registers to always be clear when invoking a hypercall. When this is found not to be the case, it triggers a consistency check in the hypervisor and causes a crash.
Fixed versions
Upgrade to a fixed version or later. Language registries are listed first, then Linux distributions, then vendor products.
| Package | Ecosystem | Fixed in |
|---|---|---|
| xen | Alpine:v3.24 | 4.18.2-r0 |
| xen | Alpine:v3.20 | 4.18.2-r0 |
| xen | Alpine:v3.23 | 4.18.2-r0 |
| xen | Alpine:v3.21 | 4.18.2-r0 |
| xen | Alpine:v3.18 | 4.17.4-r0 |
| xen | Alpine:v3.16 | 4.16.6-r0 |
| xen | Alpine:v3.19 | 4.18.2-r0 |
| xen | Alpine:v3.22 | 4.18.2-r0 |
| xen | Alpine:v3.17 | 4.16.6-r0 |
Risk scores
Affected products
| Vendor | Product | Versions |
|---|---|---|
| Alpine:v3.24 | xen | 3.2.0 |
| Alpine:v3.20 | xen | 4.2.1-r5, 0, 4.0.1-r0 |
| Alpine:v3.23 | xen | 0, 4.1.0-r0, 4.10.0-r1 |
| Alpine:v3.21 | xen | 4.17.0-r5, 4.17.1-r2, 0 |
| Alpine:v3.18 | xen | 4.2.1-r3, 4.16.1-r7, 4.2.2-r10 |
| Alpine:v3.16 | xen | 4.1.1-r0, 4.1.1-r1, 4.1.1-r2 |
| Alpine:v3.19 | xen | 4.16.1-r5, 4.0.1-r0, 4.0.1-r1 |
| Alpine:v3.22 | xen | 3.2.0, 4.14.0-r0, 4.17.0-r0 |
| Alpine:v3.17 | xen | 3.2.0, 4.2.2-r0, 4.16.2-r2 |
Timeline
- May 16, 2024 CVE Published
- Aug 7, 2026 CVE Updated
- Aug 8, 2026 Distribution Patch
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